Semiconductor wafer fabrication – the race for higher speed data processing

New technology is required by the semiconductor industry. We present a technology that is faster than any existing fab metrology systems and meets both the demands.

JAN OLAF GAUDESTAD

VP Business Development

 

Faster computers and electronic processors require smaller transistors for integrated circuits (IC), which in turn require smoother and flatter silicon wafer surfaces. The importance of traditionally acceptable sources of variation in the semiconductor manufacturing process has started to become more critical as the industry continues to push into smaller technology nodes – shrinking the transistor. The cost of each wafer keeps rising fast; it was recently revealed that Taiwan Semiconductor Manufacturing Company (TSMC) sells the 5nm node, 300mm wafer, to Apple and used in their latest iPhone 12 for $16,988 while the similar sized wafer at 7nm node sells for $9,346. The major cost driver when shrinking the transistor gate into the single digit nm node is the increased use of the $145 million extreme ultraviolet (EUV) lithography system, currently only manufactured by the Dutch company Advanced Semiconductor Materials Lithography (ASML). At the 5nm node, each EUV system is only capable of running 45,000 wafers per month. While TSMC has 2.5 million wafers per month output capacity, it is obvious that a lot of EUV systems are required to meet demand at the more advanced nodes.

Over the years, the tremendous advances in lithographic patterning capabilities has in turn driven ever-tightening control of focus (Z) and overlay (X,Y) capabilities while manufacturing the silicon chips. Process-induced overlay errors is a growing problem making new advanced wafer geometry fab tools critical for future chip makers. With current fab wafer geometry systems capable of acquiring only 700K data points on a 300mm wafer in 60 seconds, again allowing each patterned wafer geometry tool to only measure 43,200 lithography layers per month, when adding that each wafer needs 14 lithography layers at the 5nm node, wafer through put of advanced patterned wager geometry systems is just over 3,000 wafers per month. At around $15 million per system, it is not possible to fill the fab with enough tools to satisfy the output capacity required by the largest IC makers using current wafer geometry technology.  

New metrology techniques are needed to pursue the process uniformity requirements to support the future of semiconductor lithography. Wooptix has developed a new technique based on detecting the wave front phase of the light, enabling the system to acquire more than 50 million data points on each 300mm wafer in just 0.1 seconds. This extremely high speed, coupled with much higher resolution in both X, Y and Z compared to existing fab systems, makes wave front phase imaging (WFPI) the only alternative wafer geometry system capable of meeting the high speed requirements for advanced semiconductor nodes.